Exploration of RaPiD-style Pipelined FPGA Interconnects

Pipelined FPGAs promise high performance for reconfigurable computing. However, the architectural design of these systems is complex, involving the optimization of numerous features. In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of registered routing track segments, registered I/O terminals of logic units, and the flexibility of the interconnect structure on the performance of a pipelined FPGA. Our experiments with the RaPiD architecture identify tradeoffs in pipelined interconnect design. After quantifying these effects, we were able to design an architecture with a 19% improvement over RaPiD in area-delay product.